Binary Adder

Introduction

In this tutorial, we are going to look at the Binary Adder and Subtractor Circuits. We will learn about the Half Adder, Full Adder, Parallel Adder (using multiple Full Adders), Half Subtractor, Full Subtractor and a Parallel Adder / Subtractor combination circuit.

A Binary Adder is a digital circuit that performs the arithmetic sum of two binary numbers provided with any length. A Binary Adder is constructed using full-adder circuits connected in series, with the output carry from one full-adder connected to the input carry of the next full-adder.

OBJECTIVE :

To understand and implement binary Half Adder and Full Adder circuits.
To design and implement a binary adder which will add to binary words (4 bits each) using IC.

APPARATUS

Fig: Common apparatus for DLD Labs

Digital Trainer
IC's (7400, 7402, 7404, 7408, 7432, 7486)
Jumper Wire (M2M or as required)
Power Supply, Bread Board, Switches, Resistors, LEDs (When Digital Trainer Board is unavailable)
Multimeter (Trouble Shoot purposes)

Brief Theory

Digital computers perform a variety of information-processing tasks. Among the functions encountered are the various arithmetic operations. The most basic arithmetic operation is the addition of two binary digits. Adder circuit is a combinational digital circuit that is used for adding two numbers. A typical adder circuit produces a sum bit (denoted by S) and a carry bit (denoted by C) as the output. Typically, adders are realized for adding binary numbers but they can be also realized for adding other formats like BCD (binary coded decimal), XS-3 etc. Besides addition, adder circuits can be used for a lot of other applications in digital electronics like address decoding, table index calculation etc.

Fig: Simple Binary Addition

In the first three operations, each binary addition gives sum as one bit , i.e., either 0 or 1. But for the fourth addition operation (where the inputs are 1 and 1), the result consists of two binary digits. Here, the lower significant bit is called as the ‘Sum Bit’, while the higher significant bit is called as the ‘Carry Bit’.

For single bit additions, there may not be an issue. The problem may arise when we try to add binary numbers with more than one bit.

Depending on how they handle the output of the ‘1+1’ addition, they are divided into: Half Adder & Full Adder.

Half Adder

Half adder is a combinational arithmetic circuit that adds two numbers and produces a sum bit (S) and carry bit (C) as the output. If A and B are the input bits, then sum bit (S) is the XOR of A and B and the carry bit (C) will be the AND of A and B. From this it is clear that a half adder circuit can be easily constructed using one XOR gate and one AND gate.

Logical Expression :

Sum = A XOR B

Carry = A AND B

Fig: Half Adder Circuit

Half adder is the simplest of all adder circuits, but it has a major disadvantage, the half adder can add only two input bits (A and B) and has nothing to do with the carry if there is any in the input, so if the input to a half adder have a carry, then it will be neglected and adds only the A and B bits. That means the binary addition process is not complete and that’s why it is called a half adder. The truth table, schematic representation and XOR//AND realization of a half adder are shown in the figure above.

Full Adder

Full Adder is the adder which adds three inputs and produces two outputs. The first two inputs are A and B and the third input is an input carry as C-IN. The output carry is designated as C-OUT and the normal output is designated as S which is SUM. A full adder logic is designed in such a manner that can take eight inputs together to create a byte-wide adder and cascade the carry bit from one adder to the another.

Logical Expression :

SUM = (A XOR B) XOR Cin = (A ⊕ B) ⊕ Cin

CARRY-OUT = A AND B OR Cin(A XOR B) = A.B + Cin(A ⊕ B)

Fig: Full Adder Circuit

Fig: Full Adder Truth Table

Parallel Adder

As we discussed, a single Full Adder performs the addition of two one bit numbers and also the carry input. For performing the addition of binary numbers with more than one bit, more than one full adder is required and the number of Full Adders depends on the number bits. Thus, a Parallel Adder, is a combination of Multiple Full Adders and is used for adding all bits of the two numbers simultaneously.

The following figure shows a Parallel 4-bit Binary Adder, which has three full adders and one half adder. The two binary numbers to be added are ‘A3 A2 A1 A0‘ and ‘B3 B2 B1 B0‘ , which are applied to the corresponding inputs of the Full Adders. This parallel adder produces their result as ‘C4 S3 S2 S1 S0‘ , where C4 is the final carry.

Fig: A 4 bit Adder Simulation in Proteus

Commonly, the Full Adders are designed in dual in-line package integrated circuits. 74LS283 is a popular 4-bit full adder IC. Arithmetic and Logic Unit or ALU of an unit computer consist of these parallel adders to perform the addition of binary numbers. In our lab task- 3 below , we will investigate this chip.